PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 93

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
After RESET, the QuadFALC is initialized for doubleframe format with register values
listed in Table 9.
Table 9
Initial Values after RESET
Register
FMR0
FMR1
FMR2
SIC1
SIC2,
SIC3
LOOP
XSW
XSP
TSWM
XC0
XC1
RC0
RC1
IDLE
ICB 1 … 4
LIM0
LIM1
PCD
PCR
XPM2-0
IMR0-4
RTR1-4
TTR1-4
GCR
CMR1
Reset Value Meaning
00
00
00
00
00
00
40
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
FF
00
00
00
00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H,
H,
H,
H
H
H,
H,
00
FF
FF
03
H,
H
H,
H,
, 9C
00
FF
H,
H,
H
NRZ Coding, no alarm simulation.
PCM 30 – doubleframe format, 2 MBit/s system data rate,
no AIS transmission to remote end or system interface,
Payload Loop off.
8.192 MHz system clocking rate, Rec. Buffer 2 Frames,
Transmit Buffer bypass, Data sampled or transmitted on
the falling edge of SCLKR/X, Automatic freeze signaling,
data is active in the first channel phase
Channel loop back and single frame mode are disabled.
All bits of the transmitted service word are cleared (bit 2
excl.). Spare bit values are cleared.
No transparent mode active.
The transmit clock offset is cleared.
The transmit time-slot offset is cleared.
The receive clock slot offset is cleared.
The receive time-slot offset is cleared.
Idle channel code is cleared.
Normal operation (no ‘Idle Channel’ selected).
Slave Mode, Local Loop off
Analog interface selected, Remote Loop off
Pulse Count for LOS Detection cleared
Pulse Count for LOS Recovery cleared
Transmit Pulse Mask
All interrupts are disabled
No time-slots selected
Internal second timer, Power on of all 4 single FALC
channels,
DCO-R reference clock: channel 1, RCLK output: DPLL
clock, DCO-X enabled, DCO-X internal reference clock
93
Operational Description E1
PEB 22554
09.98