PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 242

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• XBS1/0 = 11 : short buffer or 96 bits :
The functions of the transmit buffer are:
• Clock adaption between system clock (SCLKX/R) and internally generated transmit
• Compensation of input wander and jitter.
• Frame alignment between system frame and transmit route frame
• Reporting and controlling of slips
Writing of received data from XDI is controlled by SCLKX/R and SYPX / XMFS in
conjunction with the programmed offset values for the transmit time-slot/clock-slot
counters. Reading of stored data is controlled by the clock generated by DCO-X
circuitry or the externally generated TCLK and the transmit framer. With the dejittered
clock data is read from the transmit elastic buffer and are forwarded to the transmitter.
Reporting and controlling of slips is automatically done according to the receive
direction. Positive / negative slips are reported in interrupt status bits ISR4.XSP and
ISR4.XSN.
A re-initialization of the transmit memory is done by re-programming the transmit
time-slot counter XC1 and with the next SYPX pulse. After that, this memory has its
optimal start position.
The frequency of the working clock for the transmit system interface is programmable by
SIC1.SSC1/0 and SIC2.SSC2 in a range of 1.544 ... 12.352 MHz / 2.048 ... 16.384 MHz.
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.SPS) of the SCLKX clock. Some clocking rates allow
transmitting of time-slots / marker in different channel- phases. Each channel-phase
which should be latched on ports XDI and XP(A-D) is programmable by bits
SIC2.SICS2-0 , the remaining channel-phases are cleared resp. ignored
The following table gives an overview of the transmit buffer operating modes.
Semiconductor Group
Buffer Size
bypass
System interface clocking rate: modulo 1.544 MHz:
max. wander: 126 UI
average delay after performing a slip: 193 bits
System interface clocking rate: modulo 2.048 MHz:
Max. wander : 28 UI in channel translation mode 0; channel translation mode 1 not
supported
System interface clocking rate: modulo 1.544 MHz:
max. wander: 38 UI
average delay after performing a slip: 48 bits
route clock (XCLK) or externally sourced TCLK.
TS Offset program.
enabled
242
Functional Description T1 / J1
Slip perform.
no
PEB 22554
09.98