PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 20

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Pin Definitions and Function (cont’d)
Pin No.
8, 13, 26,
31
9, 12, 27,
30
Semiconductor Group
Symbol
SCLKR
(1-4)
RDO(1-4)
Input (I)
Output (O)
I/O + PU
O
Function
System Clock Receive
Working clock for the receive system interface
with a frequency of 16.384 / 8.192 / 4.096 /
2.048 MHz. If the receive elastic store is
bypassed SIC1.RBS1/0 the clock supplied on
this pin is ignored.
If SCLKR is configured to an output, the internal
working clock of the receive system interface
sourced by DCO-R or RCLK is output.
In system interface multiplex mode a 16.384 or
8.192 MHz clock has to be provided on
SCLKR1, which is a common clock for all 4 rec.
system interfaces.
Receive Data Out
Received data which is sent to the system
highway. Clocking off data is done with the
rising or falling edge (SIC3.RESR) of
SCLKR(1-4) or RCLK(1-4) if the receive elastic
store is bypassed. The delay between the
beginning of time-slot 0 and the initial edge of
SCLKR(1-4) (after SYPR goes active) is
determined by the values of registers RC1 and
RC0.
If received data is shifted out with higher data
rates, the active channel phase is defined by
bits SIC2.SICS2-0. In system interface
multiplex mode all 4 received datastreams are
merged into a single datastream byte or bit
interleaved on RDO1.
20
Pin Descriptions E1
PEB 22554
09.98