PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 189

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

6.2
Pin No.
83 - 74
107 -103
100 - 93
90 - 88
62
Note: All unused input pins have to be connected to a defined level
Note: PU = If not connected an internal pull-up transistor ensure high input level.
Semiconductor Group
Pin Definitions and Function
Symbol
D15 … D11
D10 … D3
D2 … D0
A9 … A0
ALE
Input (I)
Output (O)
I
I/O
I
Function
Address Bus
Address bus selects one of the internal registers
for read or write.
Data Bus
Bi-directional three-state data lines which interface
with the system’s data bus. Their configuration is
controlled by the level of pin DBW:
– 8-bit mode (DBW = 0): D0 … D7 are active.
– 16-bit mode (DBW = 1): D0 … D15 are active.
In case of byte transfers, the active half of the bus
is determined by A0 and BHE/BLE and the
selected bus interface mode (via pin IM). The
unused half is in high impedance.
For detailed information, refer to chapter 7.2.
Address Latch Enable
A high on this line indicates an address on the
external address/data bus. The address
information provided on lines A0 … A9 is internally
latched with the falling edge of ALE. This function
allows the QuadFALC to be directly connected to
a multiplexed address/data bus. In this case, pins
A0 … A9 must be externally connected to the Data
Bus pins.In case of demultiplexed mode this pin
has to be connected directly to ground or
detailed information, refer to chapter 7.2.
D8 … D15 are in high impedance and have to
be connected to
189
V
DD
or
V
SS
General Features T1
.
V
DD
or
PEB 22554
V
SS
.
V
DD
09.98
. For