PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 291

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Common Configuration Register 2 (READ/WRITE)
Value after RESET: 00
CCR2
Unused bits have to be set to logical ‘0’.
RADD…
RBFE…
RCRC…
Semiconductor Group
7
Receive Address Pushed to RFIFO
If this bit is set to ‘1’, the received HDLC address information (1 or 2
bytes, depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. This function is applicable in non-auto mode.
Receive BOM Filter Enable
Setting this bit the Bit Oriented Message (BOM) -receiver will only
accept BOM frames after detecting 7 out of 10 equal BOM pattern.
The BOM pattern is stored in the RFIFO adding a receive status byte
marking a BOM frame (RSIS.HFR) and an interrupt ISR0.RME is
generated. The current state of the BOM receiver is indicated in
register SIS.IVB. When the valid BOM pattern disappears an interrupt
ISR0.BIV is generated.
Receive CRC ON/OFF
Only applicable in non-auto mode.
If this bit is set to ‘1’, the received CRC checksum will be written to
RFIFO (CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last
bytes in the received frame, is followed in the RFIFO by the status
information byte (contents of register RSIS). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “Valid Frame” check are modified
(refer to RSIS.VFR).
H
RFT1
0
0
1
1
RFT0
0
1
0
1
RADD
291
Bit Positions in RBCL Reset by a
CMDR.RMC Command
RBC4 .
RBC3
RBC1,0
RBC0
RBFE
0
Operational Description T1 / J1
RCRC
0
XCRC
0
PEB 22554
(x0A)
09.98