PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 340

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Framer Receive Status Register 0 (Read)
FRS0
LOS…
AIS…
LFA…
Semiconductor Group
7
LOS
Loss of Signal (Red Alarm)
Detection:
This bit is set when the incoming signal has „no transitions“ (analog
interface) or logical zeros (dig. interface) in a time interval of T
consecutive pulses, where T is programmable via PCD register:
Total account of consecutive pulses: 16 < T < 4096.
Analog interface: The receive signal level where “no transition” will be
declared is defined by the programmed value of LIM1.RIL2-0.
Recovery:
Analog interface: The bit will be reset in short haul mode when the
incoming signal has transitions with signal levels greater than the
programmed receive input level (LIM1.RIL2-0) for at least M pulse
periods defined by register PCR in the PCD time interval. In long haul
mode addtionally bit RES.6 must be set for at least 250µsec.
Digital interface: The bit will be reset when the incoming data stream
contains at least M ones defined by register PCR in the PCD time
interval.
With the rising edge of this bit an interrupt status bit (ISR2.LOS) will
be set. For additionally recovery conditions refer also to register
LIM2.LOS1.
The bit will be set during alarm simulation and reset if FRS2.ESC = 0,
3, 4, 6,7 and no alarm condition exists.
Alarm Indication Signal (Blue Alarm)
This bit is set when the conditions defined by bit FMR4.AIS3 are
detected. The flag stays active for at least one multiframe.
With the rising edge of this bit an interrupt status bit (ISR2.AIS) will be
set. It will be reset with the beginning of the next following multiframe
if no alarm condition is detected.
The bit will be set during alarm simulation and reset if FRS2.ESC = 0,
3, 4, 7 and no alarm condition exists.
Loss of Frame Alignment
The flag is set if pulseframe synchronization has been lost. The
conditions are specified via bit FMR4.SSC1/0. Setting this bit will
cause an interrupt status (ISR2.LFA).
AIS
LFA
RRA
340
Operational Description T1 / J1
LMFA
0
FSRF
PEB 22554
(x4C)
09.98