PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 139

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
RS1 ... 0 …
DCS …
STF …
DXJA…
DXSS …
Select RCLK Source
These bits select the source of RCLK.
00… extracted receive clock, generated by the DPLL
01… extracted receive clock with the option in case of an active LOS
10… dejittered 2.048 MHz clock generated by the internal DCO-R
11… dejittered 8.192 MHz clock generated by the internal DCO-R
Disable Clock Switching
In Slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the
recovered route clock. In case of loss of signal LOS the DCO-R
switches automatically to the clock sourced by port SYNC. Setting
this bit automatic switching from RCLK to SYNC is disabled.
Select TCLK Frequency
Only applicable if the pin function TCLK port XP(A-D) is selected by
PC(1-4).XPC(2-0) = 011. Data on XL1/2 (XDOP/N / XOID) are
clocked off with TCLK.
0…
1…
Disable Internal Transmit Jitter Attenuation
Setting this bit disables the transmit jitter attenuation. Reading the
data out of the transmit elastic buffer and transmitting on XL1/2
(XDOP/N / XOID) is done with the clock provided on pin TCLK. In
transmit elastic buffer bypass mode the transmit clock is taken from
SCLKX, independent of this bit.
DCO-X Synchronization Clock Source
0…
2.048 MHz
8.192 MHz
The DCO-X circuitry of each channel will synchronize to the
alarm this pin is set high.
circuitry.
circuitry.
internal reference clock which is sourced by SCLKX/R or
RCLK. Since there are many reference clock opportunities the
following internal priorization in descenting order from left to
right is realized: LIM1.RL > CMR2.DXSS > LIM2.ELT > current
working clock of transmit system interface.
If one of these bits is set the corresponding reference clock is
taken.
139
Operational Description E1
PEB 22554
09.98