PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 225

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Receive Signaling Controller
Each of the four signaling controller may be programmed to operate in various signaling
modes. The QuadFALC will perform the following signaling and data link methods:
• HDLC/SDLC or LAPD Access
• CAS-Bit Robbing
Semiconductor Group
In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD
according to Q.921 will be supported. The signaling controller of the QuadFALC
performs the FLAG detection , CRC checking, address comparisson and zero
bit-removing. The received data flow and the address recognition features may be
performed in very flexible way, to satisfy almost any practical requirements.
Depending on the selected address mode, the QuadFALC may perform a 1 or 2 byte
address recognition. If a 2-byte address field is selected, the high address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values in RAH1 and RAH2 registers. According to the
ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as
COMMAND/RESPONSE bit (C/R) and will be excluded from the address comparison.
Buffering of receive data is done in a 64 byte deep RFIFO. Refer also to chapter 8.1.
In signaling controller transparent mode, fully transparent data reception without
HDLC framing is performed, i.e. without FLAG recognition, CRC checking or
bit-stuffing. This allows user specific protocol variations.
The QuadFALC offers the flexibility to extract data during certain time-slots. Any
combination of time-slots may be programmed independently for the receive and
transmit direction.
The signaling information is carried in the LSB of every sixth frame for each time-slot.
The signaling controller samples the bit stream either on the receive line side or if
external signaling is enabled on the receive system side via port RSIG. Receive
signaling data is stored in the registers RS1-12.
Optionally the complete CAS multiframe may be transmitted on pin RSIG. The
signaling data is clocked out with the working clock of the receive highway (SCLKR)
in conjunction with the rec. synchron. pulse (SYPR). Data on RSIG will be transmitted
in the last 4 bits per time-slot and are time-slot aligned to the data on RDO. In ESF
format the A,B,C,D bits are placed in the bit positions 5-8 per time-slot. In F12/72
format the A and B bits are repeated in the C and D bit positions. The first 4 bits per
time-slot could be optionally fixed high or low. The FS/DL time-slot is transmitted on
RDO and RSIG. During IDLE time-slots no signaling information is transmitted. Data
on RSIG are only valid if the freeze signaling status is inactive. With FMR1.SAIS an all
ones may be transmitted on RDO and RSIG.
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a Loss of Signal, or a
Loss of Frame Alignment or a receive slip occures. The current freeze status is output
225
Functional Description T1 / J1
PEB 22554
09.98