PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 129

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
MAS…
Line Interface Mode 1 (Read/Write)
Value after RESET: 00
LIM1
RIL2…RIL0…
7
Master Mode
0…
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS=0.
No signal will be declared if the voltage between pins RL1 and RL2
drops below the limits programmed via bits RIL2-0 and the received
data stream has no transition for a period defined in the PCD register.
The threshold where no signal will be declared is programmable via
the RIL2-0 bits depending of bit LIM0.EQON.
LIM0.EQON = 0 (short haul mode):
000 = 0.9 V
001 = 0.7 V
010 = 0.6 V
011 = 0.4 V
100 = 0.3 V
101 = 0.2 V
110 = 0.07 V
111 = 0.05 V
LIM0.EQON = 1 (long haul mode):
000 = 1.7 V
001 = 0.8 V
010 = 0.8 V
011 = 0.5 V
100 = 0.5 V
101 = 0.2 V
1
RIL2
H
interface mode. In analog line interface mode data is transfered
through the complete analog receiver.
Slave mode
Master mode on. Setting this bit the DCO-R circuitry is
frequency synchronized to the clock (2.048 MHz) supplied by
SYNC. If this pin is connected to VSS or VDD the DCO-R
circuitry is centered and no receive jitter attenuation is
performed. The generated clocks are stable.
RIL1
RIL0
129
JATT
Operational Description E1
RL
0
DRS
PEB 22554
(x37)
09.98