PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 107

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Common Configuration Register 2 (READ/WRITE)
Value after RESET: 00
CCR2
Note: Unused bits have to be set to logical ‘0’.
RADD…
RCRC…
7
– after the current data block has been read, but before the
Note: It is seen that changing the value of RFT1, 0 is possible even
RFT1
0
0
1
1
Receive Address Pushed to RFIFO
If this bit is set to ‘1’, the received HDLC address information (1 or 2
bytes, depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. This function is applicable in non-auto mode.
Receive CRC ON/OFF
Only applicable in non-auto mode.
If this bit is set to ‘1’, the received CRC checksum will be written to
RFIFO (CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last
bytes in the received frame, is followed in the RFIFO by the status
information byte (contents of register RSIS). The received CRC
checksum will additionally be checked for correctness. If non-auto
command CMDR.RMC is issued (interrupt controlled data
transfer).
H
during the reception of one frame. The total length of the
received frame can be always read directly in RBCL, RBCH
after a RPF interrupt, except when the threshold is increased
during reception of that frame. The real length can then be
inferred by noting which bit positions in RBCL are reset by a
RMC command (see table below):
RFT0
0
1
0
1
RADD
107
Bit Positions in RBCL Reset by a
CMDR.RMC Command
RBC4 .… 0
RBC3 … 0
RBC1,0
RBC0
RCRC
Operational Description E1
XCRC
0
PEB 22554
(x0A)
09.98