PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 125

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Idle Channel Code Register (Read/Write)
Value after RESET: 00
IDLE
IDL7…IDL0…
Transmit SA4-8 Register (Read/Write)
Value after RESET: 00
XSA4
XSA5
XSA6
XSA7
XSA8
XSA8…XSA4… Transmit S
7
7
XS47
XS57
XS67
XS77
XS87
IDL7
Idle Channel Code
If channel loop back is enabled by programming LOOP.ECLB=1, the
contents of the assigned outgoing channel on ports XL1/XL2 resp.
XDOP/XDON is set equal to the idle channel code selected by this
register.
Additionally, the specified pattern overwrites the contents of all
channels selected via the idle channel registers ICB1…ICB4. IDL7
will be transmitted first.
The Sa-bit register access is enabled by setting bit FMR1.ENSA = 1.
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XSA4-8 will be copied
into a shadow register. The contents will subsequently sent out in the
service words of the next outgoing CRC multiframe (or doubleframes)
if none of the time-slot 0 transparent modes is enabled. XS40 will be
sent out in bit position 4 in frame 1, XS47 in frame 15. The transmit
XS46
XS56
XS66
XS76
XS86
H
H
, 00
through the QuadFALC without any changes. The internal
information of the QuadFALC (registers XSW and XSA4-8) will
be ignored.
H
XS45
XS55
XS65
XS75
XS85
, 00
a
-Bit Data
H
, 00
XS44
XS54
XS64
XS74
XS84
H
, 00
125
H
XS43
XS53
XS63
XS73
XS83
XS42
XS52
XS62
XS72
XS82
Operational Description E1
XS41
XS51
XS61
XS71
XS81
0
0
XS40
XS50
XS60
XS70
XS80
IDL0
PEB 22554
(x2C)
(x2D)
(x2B)
(x2E)
(x2F)
(x30)
09.98