PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 326

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Global Configuration Register (Read/Write)
Value after RESET: 00
GCR
VIS…
SCI…
SES…
ECMC…
Semiconductor Group
7
VIS
Only applicable if bit GPC1.SMM is cleared. If GPC1.SMM is set
SCLKX1 of channel 1 provides the working clock for all four channels.
0…
1…
Masked Interrupts Visible
0…
1…
Status Change Interrupt
0…
1…
Select External Second Timer
0…
1…
Error Counter Mode COFA
0…
1…
SCI
H
The working clock for the transmit system interface is sourced
The working clock for the transmit system interface is sourced
Masked interrupt status bits are not visible in registers ISR0-4.
Masked interrupt status bits are visible in ISR0-4, but they are
Interrupts will be generated either on coming or going of the
The following interrupts will be activated if enabled with
internal second timer selected
external second timer selected
not defined; reserved for future applications.
A Change of Frame or Multiframe Alignment COFA is detected
by SCLKX of each channel.
internally by the working clock of the receive system interface.
SCLKX is ignored.
not visible in registers GIS and CIS.
internal interrupt source.
detecting and recovering of the internal interrupt source:
ISR2.LOS , ISR2.AIS and ISR0.PDEN
since the last re-synchronization. The events are accumulated
in the COFA event counter COEC.1-0.
Multiframe periods received in the asynchronous state are
accumulated in the COFA event counter COEC.7-2.
An overflow of each counter is disabled.
SES
ECMC
326
Operational Description T1 / J1
0
PD
PEB 22554
(x46)
09.98