PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 167

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Receive Sa4-Bit Register (Read)
RSA4
RSA5
RSA6
RSA7
RSA8
RS47…RS40…
RS57…RS50…
RS67…RS60…
RS77…RS70…
RS87…RS80…
Semiconductor Group
7
RS47
RS57
RS67
RS77
RS87
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
Receive Sa4-Bit Data (Y-Bits)
Receive Sa5-Bit Data
Receive Sa6-Bit Data
Receive Sa7-Bit Data
Receive Sa8-Bit Data
This register contains the information of the eight SAx bits (x = 4 - 8)
of the previously received CRC multiframe. These registers will be
updated with every multiframe begin interrupt ISR0.RMB.
RS40 is received in bit-slot 4 of every service word in frame 1, RS47
in frame 15
RS50 is received in bit-slot 5, time-slot 0, frame 1, RS57 in frame 15
RS60 is received in bit-slot 6, time-slot 0, frame 1, RS67 in frame 15
RS70 is received in bit-slot 7, time-slot 0, frame 1, RS77 in frame 15
RS80 is received in bit-slot 8, time-slot 0, frame 1, RS87 in frame 15
Valid if CRC multiframe format is enabled by setting bits
FMR2.RFS1 = 1 or FMR2.RFS1/0 = 01 (Doubleframe format).
167
Operational Description E1
0
RS40
RS50
RS60
RS70
RS80
PEB 22554
(x5C)
(x5D)
(x5E)
(x5F)
(x60)
09.98