PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 45

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Reporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is
converted into bit-parallel data which is circularly written to the elastic buffer using
internally generated Receive Route Clock (RCLK).
Reading of stored data is controlled by the System Clock sourced by SCLKR or by the
receive jitter attenuator and the Synchronous Pulse (SYPR) in conjunction with the
programmed offset values for the receive time-slot/clock-slot counters. After conversion
into a serial data stream, the data is given out via port RDO. If the receive buffer is
bypassed programming of the time-slot offset is disabled and data is clocked off with
RCLK instead of SCLKR.
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 128 or 46 bits. In bypass mode the time-slot assigner is disabled. In this
case SYPR programmed as input is ignored. Slips will be performed in all buffer modes
except the bypass mode. After a slip is detected the read pointer is adjusted to one half
of the current buffer size.
The following table gives an overview of the receive buffer operating mode .
1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.
In single frame mode ( SIC1. RBS) , values of receive time-slot offset (RC1/0) have to be
specified great enough to prevent too great approach of frame begin (line side) and
frame begin (system side).
Figure 15 gives an idea of operation of the receive elastic buffer:
A slip condition is detected when the write pointer (W) and the read pointer (R) of the
memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a
slip condition is detected, a negative slip (one frame or one half of the current buffer size
is skipped) or a positive slip (one frame or one half of the current buffer size is read out
twice) is performed at the system interface, depending on the difference between RCLK
and the current working clock of the receive backplane interface. i.e. on the position of
Semiconductor Group
Buffer Size
(SIC1.RBS1/0)
bypass
short buffer
1 frame
2 frames
1)
not recommended,
enabled
TS Offset program.
(RC1/0) + SYPR = input
disabled
recom. SYPR = output
not recommended,
recom. SYPR = output
recom. SYPR = output
45
Slip perform.
no
yes
yes
yes
Functional Description E1
PEB 22554
09.98