PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 261

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PEB 22554
Functional Description T1 / J1
will not be overwritten by internal or external sourced bit robbing and Zero Code
Suppression (B7 stuffing) information.
In-Band Loop Generation and Detection
The QuadFALC generates and detects a framed or unframed in-band loop up/actuate
(00001) - and down/deactuate (001) pattern according to ANSI T1. 403 with bit error
rates as high as 1/100. Framed or unframed in-band loop code is selected by
LCR1.FLLB . Replacing the in-band loop codes with transmit data is done by FMR5.XLD
/ XLU.
The QuadFALC also offers the ability generating and detecting of a flexible in-band loop
up - and down pattern (LCR1.LLBP = 1). The loop up and loop down pattern is individual
programmable from 2 to 8 bit in length (LCR1.LAC1/0 and LCR1.LDC1/0). Programming
of loop codes is done in registers LCR2 and LCR3.
Status and interrupt-status bits will inform the user whether loop up - or loop down code
was detected.
Transparent Mode
The transparent modes are useful for loopbacks or for routing data unchanged through
the QuadFALC.
In receive direction, transparency for ternary or dual / single rail unipolar data is always
achieved if the receiver is in the synchronous state. All bits in F-bit position of the
incoming multiframe are forwarded to RDO and inserted in the FS/DL time-slot or in the
F-bit position. In asynchronous state the received data may be transparently switched
through if bit FMR2.DAIS is set. Setting of bit FMR2.RTM disconnects control of the
elastic buffer from the receiver. The elastic buffer is now in a “free running” mode without
any possibility to actualize the time slot assignment to a new frame position in case of
re-synchronization of the receiver. Together with FMR2.DAIS this function may be used
to realize undisturbed transparent reception.
Setting bit FMR4.TM switches the QuadFALC in transmit transparent mode:
In transmit direction bit 8 of the FS/DL time-slot from the system highway (XDI) is
inserted in the F-bit position of the outgoing frame. For complete transparency the
internal signaling controller, IDLE code generation, AIS alarm generation, single channel
and payload loop back has to be disabled and “Clear Channels” have to be defined via
registers CCB1 3.
Pulse Density Detection
The QuadFALC examines the receive data stream on the pulse density requirement
which is defined by ANSI T1. 403. More than 14 consecutive zeros or less than N ones
in each and every time window of 8(N+1) data bits where N=23 will be detected.
Semiconductor Group
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