PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 195

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Pin Definitions and Function (cont’d)
Pin No.
133
134
48
69
119, 130,
47, 61
Semiconductor Group
Symbol
MCLK
NC
SEC
FSC
SEC
RCLK(1-4)
SYNC
Input (I)
Output (O)
I
I + PU
I +PU
O
O
I/O+PU
Function
Reference Clock 1.544 MHz
A reference clock of 1.544 MHz +/- 50 ppm must
be provided to this pin.
Not connected
Clock Synchronization
If a clock is detected at the SYNC pin the
DCO-Rs of the QuadFALC synchronizes to this
clock 1.544 MHz or 2.048 MHz (if
LIM1.DCOC = 1). This pin has an integrated pull
up resistor.
Second Timer Input
A pulse with logical one for at least two
1.544 MHz cycles will trigger the internal second
timer.
Enabled with GPC1.FSS2-0 an 8-kHz Frame
Synchronization Pulse is output via this pin. The
synchronization pulse is active high / low for one
1.544 / 2.048 MHz cycle (pulse width = 648 / 488
ns).
Second Timer Output
Activated high every second for two 1.544 MHz
clock cycles. Enabled with GPC1.CSFP1-0.
Receive Clock
After Reset this port is configured to an input.
Setting of bit PC5.CRPwill switch this port to an
output. Input function not defined.
Output function:
CMR1.RS1/0 = 00: Receive Clock extracted from
the incoming data pulses. Frequency: 1544 kHz
CMR1.RS1/0 = 01: RCLK is set high in case of
loss of signal (FRS0.LOS=1).
Optional one of the dejittered system clocks
sourced by DCO-R is clocked out. Clock
frequency: 1544 / 6176 or 2048 / 8192 kHz.
Selected by CMR1.RS1/0=11.
Wih GPC1.R1S1/0 one of the four RCLK(1-4) is
output on RCLK1.
195
General Features T1
PEB 22554
09.98