PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 361

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

ES…
SEC…
LLBSC…
RSN…
RSP…
Semiconductor Group
Errored Second
This bit is set if at least one enabled interrupt source via ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected
FER = Framing error received
CER= CRC error received
AIS = Alarm indication signal (blue alarm)
LOS = Loss of signal (red alarm)
CVE = Code violation detected
SLIP= Transmit Slip or Receive Slip positive/negative detected
Second Timer
The internal one second timer has expired. The timer is derived from
clock RCLK.
Line Loop Back Status Change / PRBS Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM=0: This bit is set to one, if the LLB actuate signal or the
LLB deactuate signal respective is detected over a period of 33,16
msec with a bit error rate less than 1/100.
The LLBSC bit is also set to one, if the current detection status is left,
i.e., if the bit error rate exceeds 1/100.
The actual detection status can be read from the FRS1.LLBAD and
FRS1.LLBDD, respective.
PRBS Status Change
LCR1.EPRM=1: With any change of state of the PRBS synchronizer
this bit will be set. The current status of the PRBS synchronizer is
indicated in FRS1.LLBAD.
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency
of the receive system interface working clock based on 1.544 MHz. A
frame will be skipped. It will be set during alarm simulation.
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of
the receive system interface working clock based on 1.544 MHz. A
frame will be repeated. It will be set during alarm simulation.
361
Operational Description T1 / J1
PEB 22554
09.98