PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 78

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Second timer
In-Band Loop Generation and Detection
The QuadFALC generates and detects a framed or unframed in-band loop up/actuate
- and down/deactuate pattern with bit error rates as high as 1/100. Framed or unframed
in-band loop code is selected by LCR1.FLLB . Replacing transmit data with the in-band
loop codes is done by FMR3.XLD / XLU.
The QuadFALC also offers the ability generating and detecting of a flexible in-band loop
up - and down pattern (LCR1.LLBP = 1). The loop up and loop down pattern is individual
programmable from 2 to 8 bit in length (LCR1.LAC1/0 and LCR1.LDC1/0). Programming
of loop codes is done in registers LCR2 and LCR3.
Status and interrupt-status bits will inform the user whether loop up - or loop down code
was detected.
Time-Slot 0 Transparent Mode
The transparent modes are useful for loopbacks or for routing data unchanged through
the QuadFALC.
In receive direction, transparency for ternary or dual / single rail unipolar data is always
achieved if the receiver is in the synchronous state. In asynchronous state the data may
be transparently switched through if bit FMR2.DAIS is set. However, correct time-slot
assignment can not be guaranteed due to missing frame alignment between line and
system side.
Setting of bit FMR2.RTM disconnects control of the internal elastic store from the
receiver. The elastic buffer is now in a “free running” mode without any possibility to
actualize the time slot assignment to a new frame position in case of re-synchronization
of the receiver. Together with FMR2.DAIS this function can be used to realize
undisturbed transparent reception.
Transparency in transmit direction can be achieved by activating the time-slot 0
transparent mode (bit XSP.TT0 or TSWM.7-0). If XSP.TT0 = 1 all internal information of
Semiconductor Group
alarm indication signal , E bit error , receive and transmit slips.
With a programmable interrupt mask register ESM all these alarms or error events
could generate an Errored Second interrupt (ISR3.ES) if enabled.
Additionally per channel a one second timer interrupt could be internally generated to
indicate that the enabled alarm status bits or the error counters have to be checked.
If enabled via bit GPC1.FSS2-0 the one second timer of the selected channel can be
output on port SEC/FSC (GPC1.CSFP1/0). Optionally if all four channels of the
QuadFALC should synchronized to an external second timer an appropriate clock has
to be provided to pin SEC/FSC. Selecting the external second timer is done with
GCR.SES. Refer also to register GPC1.
78
Functional Description E1
PEB 22554
09.98