PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 88

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.1.3
Shared Flags
The closing Flag of a previously transmitted frame simultaneously becomes the opening
Flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting bit SFLG in control register CCR1.
Transparent Transmission and Reception
When programmed in the extended transparent mode via the MODE register (MDS2-
0 = 111), the QuadFALC performs fully transparent data transmission and reception
without HDLC framing, i.e. without
• FLAG insertion and deletion
• CRC generation and checking
• Bit-stuffing
In order to enable fully transparent data transfer, bit MODE.HRAC has to be set.
Received data is always shifted into RFIFO.
Data transmission is always performed out of XFIFO by directly shifting the contents of
XFIFO in the outgoing datastream. Transmission is initiated by setting CMDR.XTF (04
A synch-byte FF
transmitted.
Cyclic Transmission (fully transparent)
If the extended transparent mode is selected, the QuadFALC supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to XFIFO, the command XREP.XTF via the CMDR
register (bit 7
in XFIFO repeatedly to the remote end.
Note: The cyclic transmission continues until a reset command (CMDR: SRES) is issued
CRC ON/OFF Features
As an option in HDLC mode the internal handling of received and transmitted CRC
checksum can be influenced via control bits CCR3.RCRC and CCR3.XCRC.
• Receive Direction
Semiconductor Group
The received CRC checksum is always assumed to be in the 2 (CRC-ITU) last bytes
of a frame, immediately preceding a closing flag. If CCR3.RCRC is set, the received
CRC checksum will be written to RFIFO where it precedes the frame status byte
(contents of register RSIS). The received CRC checksum is additionally checked for
or with resetting CMDR.XREP, after which continuous ‘1’-s are transmitted.
During cyclic transmission the XREP-bit has to be set with every write operation to
CMDR.
Signaling Controller Functions
0 = ‘00100100’ = 24
H
is automatically sent before the first byte of the XFIFO will be
H
) forces the QuadFALC to transmit the data stored
88
Operational Description E1
PEB 22554
09.98
H
).