PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 49

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

3.5
The QuadFALC offers a flexible feature for system designers where for transmit and
receive direction different system clocks and system pulses are necessary. The interface
to the receive system highway is realized by two data buses, one for the data RDO and
one for the signaling data RSIG. The receive highway is clocked via pin SCLKR, while
the interface to the transmit system highway is independently clocked via pin SCLKX.
The frequency of these working clocks and the data rate of 2.048 / 4.096 / 8.192 / 16.384
MBit/s for the receive and transmit system interface is programmable by SIC1.SSC1/0 ,
and SIC1.SSD1, FMR1.SSD0. Selectable system clock and data rates and their valid
combinations are shown in the table below
Table 4
System Clocking and Data Rates
System Data Rate
x = valid , -- = invalid
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow
transmitting of time-slots in different channel- phases. Each channel-phase which should
be active on ports RDO, XDI, RP(A-D) and XP(A-D) is programmable by SIC2.SICS2-0,
the remaining channel-phases are cleared or ignored.
The signals on pin SYPR in conjunction with the assigned timeslot offset in register RC0
and RC1 will define the beginning of a frame on the receive system highway.The signal
on pin SYPX in conjunction with the assigned timeslot offset in register XC0 and XC1 will
define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time-slot 0, bit 0) relative to SYPR/X is possible in the range
of 0 - 125 µsec. The minimum shift of varying the time-slot 0 begin could be programmed
between 1 bit and 1/8 bit depending of the system clocking and data rate. e.g. with a
clocking / data rate of 2.048 MHz shifting is done bitwise, while running the QuadFALC
with 16.384 MHz and 2.048 MBit/s data rate it is done by 1/8 bit.
A receive frame marker RFM could be activated during any bit position of the entire
frame. Programming is done with registers RC1/0. The pin function RFM is selected by
PC(1-4).RPC(2-0) = 001. The RFM selection disables the internal time-slot assigner, no
offset programming is performed. The receive frame marker is active high for one
Semiconductor Group
2.048 MBit/s
4.096 MBit/s
8.192 MBit/s
16.384 MBit/s
System Interface
Clock Rate
2.048 MHz
x
--
--
--
Clock Rate
4.096 MHz
x
x
--
--
49
Clock Rate
8.192 MHz
x
x
x
--
Functional Description E1
x
Clock Rate
16.384 MHz
x
x
x
PEB 22554
09.98