MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 465

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
full-duplex transmission — Communication on a channel in which data can be sent and
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing
input/output (I/O) — Input/output interfaces between a computer system and the external world.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
inter-IC bus (I
interrupt — A temporary break in the sequential execution of a program to respond to signals
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
I/O — See “input/output (I/0).”
jitter — Short-term signal instability.
MC68HC912DT128A — Rev 4.0
MOTOROLA
over to zero and begins counting again.
received simultaneously.
through F.
modes, the CPU uses the contents of IX or IY to determine the effective address of the
operand. IX and IY can also serve as a temporary data storage locations.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
of data exchange between devices.
from peripheral devices by executing a subroutine.
execute a subroutine.
2
C) — A two-wire, bidirectional serial bus that provides a simple, efficient method
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Glossary
Technical Data
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