Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 12

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
DS0200-003
Figure 2-1: Reset Module Block Diagram......................................................................................................... 7
Figure 3-1: Simplified PMU Block Diagram ....................................................................................................... 8
Figure 3-2: Main Crystal External Circuits ....................................................................................................... 10
Figure 3-3: System Clocking ............................................................................................................................. 10
Figure 7-1: CS1 as A[24] .................................................................................................................................... 30
Figure 7-2: Single Read/Write Timing Diagram ............................................................................................. 31
Figure 7-3: Asynchronous Page Read Timing Diagram............................................................................... 32
Figure 7-4: flclk Based Timing Diagram........................................................................................................... 33
Figure 7-5: External Memory Example ............................................................................................................ 37
Figure 7-6: Connection to an 8-bit SRAM Device ........................................................................................ 38
Figure 7-7: Connection to a 16-bit SRAM Device......................................................................................... 38
Figure 7-8: Connection to a 16-bit SRAM Device with Byte Enable.......................................................... 38
Figure 7-9: Connection to 2 x 8-bit SRAM Devices....................................................................................... 39
Figure 7-10: Connection to an 8-bit FLASH Device ...................................................................................... 39
Figure 7-11: Connection to a 16-bit FLASH Device ...................................................................................... 39
Figure 7-12: Sync Burst Flash Configuration (AM29BL802C)........................................................................ 40
Figure 7-13: Connection to two 4M byte x 8-bit FLASH Devices................................................................ 40
Figure 8-1: Acknowledge Waveform ............................................................................................................. 53
Figure 9-1: Magnetic Card Bit encoding ....................................................................................................... 60
Figure 9-2: Peak Detection Algorithm ............................................................................................................ 61
Figure 10-1: SPI Data Transfer ........................................................................................................................... 69
Figure 10-2: State Diagram for Smart Card Controller ................................................................................ 72
Figure 11-1: RTC Crystal External circuit ......................................................................................................... 94
Figure 11-2: APB Lock State Machine............................................................................................................. 99
Figure 15-1: LCD controller Read/Write Cycles .......................................................................................... 110
Figure 16-1: Interrupt and RESET Timing Diagram ....................................................................................... 113
Figure 16-2: Auto baud Timing Diagram...................................................................................................... 125
Figure 17-1: Infrared System Block Diagram................................................................................................ 131
Figure 17-2: Infrared Data transmission ........................................................................................................ 132
Figure 17-3: Infrared Data Reception........................................................................................................... 132
Figure 18-1: SPI Configured as a Master in a Single Master, Single Slave System................................. 143
Figure 18-2: SPI Configured as a Master in a Single Master, Multiple Slave system ............................. 143
Figure 18-3: SPI Configured as a Slave ......................................................................................................... 144
Figure 18-4: SPI Timing (PHASE = 0)................................................................................................................ 146
Figure 18-5: SPI Timing (PHASE = 1)................................................................................................................ 147
Figure 19-1: Buffer Descriptor Entry ............................................................................................................... 156
Figure 19-2: USB Token Transaction ............................................................................................................... 157
Figure 19-3: Dual Role "B" Device Flow Diagram ........................................................................................ 159
Figure 19-4: Dual Role "A" Device Flow Diagram........................................................................................ 160
Figure 20-1: 32-bit GPIO Detailed Block Diagram ...................................................................................... 173
Figure 21-1: External Memory I/O Timing ..................................................................................................... 180
Figure 21-2: SDRAM Interface I/O Timing ..................................................................................................... 180
Figure 21-3: USB Data Signal Timing .............................................................................................................. 181
List of Figures
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