Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 141

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 17: Universal Asynchronous Receiver/Transmitter
(UART)
17.1 Functional Description
17.1.1 UART Transmitter
17.1.2 UART Receiver
DS0200-003
The UART is a fully 16550 compatible APB device that implements the logic required to support various
asynchronous communications protocols. It implements two separate 16-byte-deep DMA-supported FIFOs
for both transmission and reception. The UART module provides the following features:
There are 3 UARTs implemented in the Z32AN Series SoC.
encoder/decoder block.
The transmitter block controls the data transmitted on TXD. It implements the FIFO, accessed through
UARTx_THR, the transmit shift register, the parity generator, and logic for the transmitter to control the
protocol.
Software writes a data byte to be transmitted into UARTx_THR. In FIFO mode, up to 16-bytes can be written
at a time. Data from the FIFO is transferred to the transmit shift register at the appropriate time and
transmitted out on TXD.
After reset, UARTx_THR is empty, UARTx_LSR.THRE is ‘1’ and an interrupt is generated (if enabled).
Software can reset this interrupt by loading data into UARTx_THR.
The transmit shift register places the byte to be transmitted onto TXD serially, least-significant bit first.
Control logic within the block adds the protocol bits to the byte being transmitted. The transmitter block
obtains the parameters for the protocol from UARTx_LCR. TXD is set to ‘1’ if the transmitter is idle (it does
not contain any data to be transmitted). The transmitter operates with the BRG clock. Data bits are placed
on TXD once every 16 BRG clock cycles. The transmitter also implements a parity generator that attaches
the parity bit to the byte, if programmed.
The receiver block controls the data reception from RXD. It implements a receiver shift register, receiver line
error condition monitoring logic and receiver data ready logic. It also implements the parity checker, and
checks for overrun errors and break signals.
Software reads received data from this UARTx_RBR. The condition of UARTx_RBR is monitored via
UARTx_LSR.DR, which is set to ‘1’ a data byte is transferred to UARTx_RBR from the receiver shift register.
UARTx_LSR.DR is cleared when software reads all received data bytes. If the number of bits received is
less than eight, the unused most significant bits of the data byte read are 0. In FIFO mode, up to 16
characters can be received before an overrun condition occurs. In addition to the receive data FIFO, 16
deep FIFOs exist for holding the parity error, framing error, and receive break condition flags.
The receiver uses the clock from the BRG for receiving the data. This clock must be 16x the appropriate
baud rate. The receiver synchronizes the shift clock on the falling edge of the start bit. It then receives a
complete byte according to the set parameters.
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5-, 6-, 7-, or 8-bit data transmission
Even/odd or no parity bit generation and detection
Start and stop bit generation and detection (supports up to two stop bits)
Line break detection and generation
Receiver overrun and framing errors detection
Logic and associated I/O to provide modem handshake capability
Multi-drop mode capable
UART2 contains an additional infrared
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