Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 121

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
14.5.4 Offset 00Ch: ADC_INT – ADC Interrupt Register
DS0200-003
31:10
05:04
02:00
Bits
09
08
07
06
03
Type
RW
RW
RW
RW
RW
RW
RO
RO
Reset
000
0
0
0
0
0
0
0
Description
Reserved
Global Enable (GLBL_IE): When set, enables ADC interrupts.
FIFO Level Enable (FIFO_LEVEL):
condition.
FIFO Underflow Enable (FIFO_UNDERFLOW): When set, enables interrupts on
FIFO underflow condition.
FIFO Overflow Enable (FIFO_OVERFLOW): When set, enables interrupts on FIFO
overflow condition.
Reserved
DMA Request Enable (DMA_REQUEST_EN): When set, enables DMA requests to
the DMA controller when the number of FIFO entries is greater than the FIFO interrupt
level. This bit is not directly related to ADC interrupts.
FIFO Interrupt Level (FIFO_INT_LEVEL): Sets the number of samples in the FIFO
before ADC_STA.FIFO_LVL is set.
generate DMA requests. Encoding:
 000: One or more entries
 001: Two or more entries
 010: Three or more entries
 011: Four entries
 100–111: Invalid
This bit is also used with DMA_REQUEST_EN to
When set, enables interrupts on FIFO Level
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