Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 36

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
6.7
6.8
6.8.1
DS0200-003
Certain registers within the ARM922T may be overwritten by nested interrupts, namely SPSR and LR(R14).
These registers should be saved prior to re-enabling interrupts and restored after interrupts are re-disabled.
Refer to the ARM Architecture Reference Manual for complete information.
Interrupt Latching
Interrupts are not latched within the INTC and it is the responsibility of the ISR to perform whatever
operations are necessary to clear the interrupt at the source peripheral where it is latched. An enabled
interrupt into the INTC will be passed on to the CPU via the IRQ/FIQ signals. This interrupt will remain active
until cleared at the source or the corresponding interrupt enable bit is cleared.
Registers: Base → FFFFF000h
Offset 000h: INTC_EN – Interrupt Controller Enable Register
31:00
Bits
080h - OFCh
100h – 17Ch
Type
RW
Offset
00Ch
01Ch
000h
004h
008h
010h
014h
018h
020h
024h
028h
F00h
F04h
F08h
F0Ch
Reset
0
INTC_SWINT_SET
INTC_SWINT_CLR
Description
Enable (EN): When set, enables the corresponding channel. Bit 0 enables channel 0,
Bit 1 enables channel 1, etc. These bits can be set or cleared by writing directly to it, or
by writing to INTC_ESET and INTC_ECLR.
INTC_SWINT
INTC_CFGN
INTC_RSTA
INTC_IDBG
INTC_FDBG
INTC_VECN
INTC_FEND
INTC_ESET
INTC_ECLR
INTC_DFLT
INTC_FVEC
INTC_IEND
INTC_ISTA
INTC_IVEC
Register
INTC_EN
Description
Interrupt Enable Register
Interrupt Enable Set Register
Interrupt Enable Clear Register
Default Vector
Interrupt Status Register
Raw (Unmasked) Interrupt Status Register
IRQ Processor Debug Register
FIQ Processor Debug Register
Software interrupt register
Software interrupt set register
Software interrupt clear register
Channel “N” Vector Register (N = 0 to 31)
Channel “N” Configuration Register (N = 0 to
31)
IRQ Vector Register
FIQ Vector Register
IRQ End-of-Interrupt Register
FIQ End-of-Interrupt Register
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