Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 86

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
10.2.4 Timing Checker
10.2.4.1
10.2.4.2
10.2.4.3
10.2.4.4
10.2.4.5
10.2.5 Interrupt Generation
DS0200-003
This performs the mandatory checking on the Answer to Reset (ATR) delay, ATR length, Block Wait Timer
(BWT), Character Wait Time (CWT), and Work Wait Time (WWT) parameters.
The ATR is checked against 3 programmable parameters:
An ATR delay error is raised as a BWT error if a start bit is received before AtrMinDelay after the end of the
card reset or if not start bit is received before AtrMaxDelay after the end of the card reset. An ATR length
error is raised as a CWT error if the ATR end is not signaled within AtrMaxLength after the start of the ATR.
The error is cleared during a card reset or when software reads INT_STAT.
This is raised when the time between the last transmitted start bit and the next received start bit exceeds
BWT.BWT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared
during a card reset or when the software reads INT_STAT.
This is raised when the time between two consecutive received start bits exceeds CWT.CWT_TO.
COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared during a card reset
or when the software reads INT_STAT.
This is raised when the time between the last received or transmitted start bit and the next received start bit
exceeds WWT.WWT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is
cleared during a card reset or when the software reads INT_STAT.
This is raised when the time between the last transmitted start bit and the next received start bit is less than
BGT.BGT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared
during a card reset or when the software reads INT_STAT.
Interrupt generation is governed by IER and INT_EN. When an interrupt is generated, the corresponding bit
is set in LSR or INT_STAT. The status bits are cleared when the status register is read except for the TX
Shift and TX Hold Empty. TO_EN.MST_INT_EN acts directly on the interrupt line. For ease of use, the
status bits contained in the UART LSR are replicated in the controller’s INT_STAT. Reading this register
also clears LSR status bits.
ATR
Block Wait Time Error (INT_STAT.BWT)
Character Wait Time Error (INT_STAT.CWT_ERR)
Work Wait Time Error (INT_STAT.WWT_ERR)
Block Guard Time Error (INT_STAT.BGT_ERR)
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DeacStopClock: The card clock is stopped and the controller moves to DeacLowerIO.
DeacLowerIO: The IO line is pulled ‘0’ and the controller moves to DeacPowerOff.
DeacPowerOff: The card is powered off and the controller moves to Idle.
AtrMinDelay: Minimum delay between card reset end and ATR start in card clock units.
AtrMaxDelay: Maximum delay between card reset end and ATR start in card clock units.
AtrMaxLength: Maximum ATR length in ETU units. It is up to the software to notify the Smart
Card block of the ATR end with an AtrEnd command.
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