Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 123

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 15: LCD Interface
15.1 Interface Timing
15.1.1 Read Cycle
15.1.2 Write Cycle
DS0200-003
The LCD interface is an APB device providing an interface to an external LCD display. The attached display
controller may be character or pixel based, and it may support only black and white, or full color. Features:
The following figure is a timing diagrams for read and write cycles generated by the LCD interface In the
following figure, LCD_E is shown programmed as active Low.
Read cycles are generated by the LCD interface whenever there is a pending read request through the
LCD_RD register.
Write cycles are generated automatically by the LCD interface whenever there is a pending write in
LCD_WR and there is no pending read. The values for T
through LCD_CFG. Values for T
respectively (for exact parameters, see section Chapter 21:. The polarity of LCD_E is also programmable.




Directly compatible with popular LCD display, text, and graphics modes.
Supports interfaces of 4-bit or 8-bit data and 3 controls.
Read and writes to external LCD module supported register operations.
Programmable read and write cycle times.
LCD_E
LCD_RnW
LCD_RS
LCD_D[7:0]
LCD_E
LCD_RnW
LCD_RS
LCD_D[7:0]
Figure 15-1: LCD controller Read/Write Cycles
D-SETUP
T
T
setup
setup
and T
Write Cycle Timing
D-HOLD
Read Cycle Timing
VALID WRITE DATA
T
T
en
en
are not programmable and are nominally 10ns and 0ns,
T
D-setup
SETUP
VALID
DATA
T
hold
, T
T
hold
HOLD
T
D-hold
T
T
dis
dis
, T
EN
, and T
DIS
are programmable
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