Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 23

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
3.3
3.4
DS0200-003
Main Oscillator External Circuits
The required crystal circuit for the main oscillator is shown below. Supported crystal frequencies are 14MHz
- 40MHz..
To allow the oscillator to stabilize, the PMU has a 16-bit ripple counter which will block the first 64k crystal
clock cycles after a power on reset or when the crystal is re-enabled by a wake function.
System Clocking Notes
The system outlined in Figure 4-3 isolates sysclk from any glitches or over/under-clocking:
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USB Wake: USB can return the SoC to active operation from Idle or Stop Modes. The lowest
power for USB suspend is achieved through “stop” mode. The PMU can be configured to wake
when USB activity is detected.
Fast glitches (< 20ns) are prevented from entering the system by the 20ns Glitch Filter
between the oscillator and the rest of the system. This limits the output of the oscillator from
generating a signal faster than 50MHz. This is in effect whether or not sysclk is derived from
the PLL.
Fast frequency over-clocking is prevented by the PLL losing lock in the event of sudden
changes to the input clock frequency. This is only operate when sysclk is derived from the PLL.
Under-clocking is prevented by the PLL losing lock when the input clock is below the minimum
requirement of the PLL. This will operate only when sysclk is derived from the PLL.
Figure 3-2: Main Crystal External Circuits
Figure 3-3: System Clocking
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