Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 129

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
16.2.1.3
16.2.1.4
DS0200-003
If an value other than 0001h is loaded into Tx, use the one-shot mode equation to determine the first time-
out period.
In Counter mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the
GPIO Port pin Timer Input function. The TPOL bit in the Timer Control Register selects whether the count
occurs on the rising edge (TPOL = “0”) or the falling edge (TPOL = “1”) of the Timer Input signal. In Counter
mode, the pre-scalar is disabled. Any value assigned to PRES in Counter Mode will have no effect. The
input frequency of the Timer Input signal must not exceed one-fourth the hclk frequency.
Upon reaching the Compare value stored in the Timer Compare register, the timer generates an interrupt,
the count value in the Timer register is reset to 0001H and counting resumes. Also, if the Timer Output
function is enabled in the GPIO, the Timer Output pin changes state from Low to High or from High to Low at
Timer Compare.
The steps for configuring a timer for Counter mode and initiating the count are as follows:
In Counter mode, the number of Timer Input transitions since the timer start is given by the following
equation:
In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin.
The timer input is the hclk. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM
register. When the timer count value matches the PWM value, the timer output toggles. The timer continues
counting until it reaches the Compare value stored in the Timer Compare register. Upon reaching the
Compare value, the Timer Output signal toggles again, the timer generates an interrupt, the count value in
the Timer register is reset to 0001H and counting resumes.
The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows:
Counter Mode
PWM Mode
1.
2.
3.
4.
5.
6.
7.


1.
2.
Clear TxCTL.TEN, Write TxCTL.TMODE to “010”, and set TxCTL.PRES. Select either the
rising or falling edge of the timer input signal for the count via TPOL:
Write to the Timer register to set the starting count value. This only affects the first pass in
Counter mode. After the first Timer Compare in Counter mode, counting always begins at the
reset value of 0001H. Generally, in Counter mode, the Timer register should be written with the
value 0001H.
Write to the Timer Compare register to set the Compare value.
If desired, enable the timer interrupt (via the Interrupt Mask Register in the Interrupt Controller)
and set the timer interrupt priority (by writing to the appropriate Configuration Table Register in
the Interrupt Controller herein).
Configure the associated GPIO port pin for the Timer Input function.
If using the Timer Output function, configure the associated GPIO port pin for the Timer Output
function. See chapter covering GPIO.
Write to the Timer Control register to enable the timer (TEN = “1”).
TxCTL.TPOL = “0”: Timer Output signal begins as a Low (“0”) and then transitions to a High
(“1”) when the timer value matches the PWM value. The Timer Output signal returns to a Low
(“0”) after the timer reaches the Compare value, which is reset to 0001H.
TxCTL.TPOL = “1”: Timer Output signal begins as a High (“1”) and then transitions to a Low
(“0”) when the timer value matches the PWM value. The Timer Output signal returns to a High
(“1”) after the timer reaches the Compare value, which is reset to 0001H.
Clear TxCTL.TEN, Write TxCTL.TMODE to “010”, and set TxCTL.PRES. Select the initial
logic level and PWM high/low transition for the timer output function via TPOL:
Write to the Timer register to set the starting count value (typically 0001H). This only affects
the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins
at the reset value of 0001H.
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