Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 120

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
14.5.2 Offset 004h: ADC_CMD – ADC Command Register
14.5.3 Offset 008h: ADC_FIFO – ADC FIFO
DS0200-003
31:07
06:04
31:13
12:10
09:00
Bits
Bits
03
02
01
00
Type
Type
RW
RW
RW
RW
RO
RO
RO
RO
RO
Reset
Reset
000h
000
000
0
0
0
0
0
0
Description
Reserved
Rotation Limit (ROT_LIMIT): Indicates how many A-H Channel Select are involved
in the rotation of continuous sampling. These bits are only effective in the continuous
sample mode.
Reserved
Continuous Sample (CONT_SMPL): When set, enters continuous sample mode.
This bit has lower priority than the single sample control.
Single Sample (SNGL_SMPL): When set, initiates a single conversion.
sample input pin is selected from ADC_IN[4:1] as programmed in the A-CH SEL bits of
ADC_CFG. This bit always reads 0. This bit has no effect if Continuous Sample is
enabled.
ADC Reset (ADC_RST): When set, resets the FIFO and status bits of ADC, and holds
the ADC in reset until this bit is cleared to ‘0’.
Description
Reserved
Sample Pin (SMPL_PIN): These bits indicate the ADC_IN[4:1] pin associated with
the ADC Sample. In case of an underflow, the content is undefined.
ADC Sample (SAMPLE): 10-bit ADC sample that has been moved into the FIFO. If
the FIFO is empty, the underflow bit is set and the content is undefined.
 0: A Channel only
 1: A, B Channels
 2: A, B, C Channels
 3: A, B, C, D Channels
 .....
 7: A, B, C, D, E, F, G, H Channels
 000: N/A
 001: Sample holds data from ADC_IN[1]
 010: Sample holds data from ADC_IN[2]
 011: Sample holds data from ADC_IN[3]
 100: Sample holds data from ADC_IN[4]
 101 - 111: N/A
The analog
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