Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 46

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
7.1.4
DS0200-003
MEMC_CFG.FCLK_DIV divides hclk to allow access to slow peripherals that do not have a READY pin.
The example provided here has settings of N
READY ignored.
Clock Divided Transactions
Symbol
t
FLCLK
t
t
t
t
t
t
t
RWI
WS
WA
WH
RH
RS
RA
Formula
Table 7-4: Extended Timing Parameters (based on MEMC_TIMN)
Figure 7-4: flclk Based Timing Diagram
Description
Clock Division: Controls the frequency of flclk by dividing hclk.
Read Setup Time: Number of flclks before nOE goes active during a read.
Read Access Time: Number of flclks after nOE active before first data sampled.
Cycle Hold Time: Number of hclks between nOE inactive and end of the cycle.
Read/Write Idle Time: Number of clocks after a read before a subsequent
write cycle, access on a different chip select, or data bus clamping can occur.
Write Setup Time: Number of clocks before nWE, A, D, and nCS active on a
write.
Write Access Time: Number of clocks before data is sampled and nOE inactive.
Write Hold Time: Number of clocks nOE is inactive before end of write cycle.
RS
=1, N
RA
=3, N
RH
=1, N
RWI
=1, N
WS
=1, N
WA
=3, N
WH
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=1 and