Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 164

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
18.9.3 Offset 08h: SPI_STA – SPI Status Register
DS0200-003
31:08
Bits
07
02
01
00
6
5
4
3
RW1C
RW1C
RW1C
RW1C
RW1C
Type
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
1
Description
Reserved
Interrupt Request (IRQ): When cleared, an interrupt request is not pending. When
set, an interrupt request is pending. If one or more of the error condition status bits is
asserted, clear those bits at the same time this bit is cleared.
Transmit Overrun (TOVR): When set, transmit overrun error has occurred.
Collision (COL): When set, a multi-master collision (mode fault) has been detected.
Slave Mode Transaction Abort (ABT):
detected.
Receive Overrun (ROVR): When set, receive overrun error has occurred.
Reserved
Transmit Status (TXST): When set, data transmission currently in progress.
Slave Select (SLAS): When set, if SPI enabled as a slave, indicates slave is not
selected. This bit only has effect when SPI is enabled as a slave.
When set, slave mode transaction abort
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