Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 126

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 16: Timers
16.1 Watchdog Timer (WDT)
16.1.1 Enabling
16.1.2 Time Delay Period Selection
DS0200-003
The WDT is an APB device that protects against conditions that may place the microcontroller into an
unsuitable operating state. When enabled, the WDT periodically sends interrupts and waits for interrupt
service. If software does not respond by servicing the interrupt within a pre-defined time and WDT reset is
enabled, the WDT sends a system reset request to the Power Management Unit (PMU). The WDT features
sixteen programmable time delay periods, 2
Timer is shown below.
Software sets WDT_CTL.WDT_EN to ‘1’ to enable the WDT. The WDT can be disabled by system reset or
clearing WDT_CTL.WDT_EN to ‘0’.
WDT_CTL.INT_EN and WDT_CTL.RST_EN.
There are two independent time delay periods can be specified in the WDT, an “interrupt period”, which
specifies the time delay before the WDT sends an interrupt to the CPU, and a “reset period”, which specifies
the time delay before the WDT sends a system reset request to the PMU if the interrupt is not serviced.
After the interrupt is generated, software services it with a sequence of writes to WDT_RR. If the interrupt is
not serviced within this timeframe and the WDT reset is enabled, the WDT sends a system reset request
(RESET) to the PMU. Figure 15-1 shows the timing diagrams for interrupt and reset.
There are sixteen choices of time delay periods for the WDT—2
delay for a specific clock source can be calculated by the following equation:
Up Counter
Interrupt
32-Bit
RESET
Table 16-1: Watchdog Timer Approximate time Delays
Clock Source
90 MHz hclk
90 MHz hclk
Figure 16-1: Interrupt and RESET Timing Diagram
90 MHz hclk
90 MHz hclk
0 1 2 3
INT_PERIOD
Interrupt and reset from the WDT is controlled through
16
. . .
through 2
Divider Value
RST_PERIOD
2
2
2
2
18
22
25
27
31
clock cycles. The architecture for the Watchdog
16
, 2
17
, 2
Time Delay
0 1 2
18
Completion of Service
47ms
Routine
, through 2
3ms
0.4s
1.5s
31
hclk cycles. The time
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