Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 181

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
19.8.13 Offset 090h: USB_STAT – USB Status Register
19.8.14 Offset 094h: USB_CTRL – USB Control Register
DS0200-003
31:08
Bits
31:08
07:04
01:00
Bits
07
06
05
04
03
02
01
00
03
02
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RO
RO
RO
RO
RO
RO
Reset
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
J-State (J): USB differential receiver JSTATE. Polarity is affected by USB_ADDR.LS.
Single Ended Zero (SE0): Live USB Single Ended Zero signal.
Transmit Suspend (device) / Token Busy (host) (SUS_BSY): When set as a
device, the controller has disabled packet transmission and reception. Clearing this bit
allows the controller to continue token processing. This bit is set when a Setup Token is
received.
commands must be written.
Reset (RESET): When set, the controller performs USB reset signaling. Only valid in
host mode. Software must set this bit to ‘1’ for the required amount of time and then
clear it back to ‘0’. For more information on RESET signaling see the USB specification.
Host Enable (HOST): When set, enables the controller to operate as a host.
Resume (RESUME): When set, the controller executes resume signaling. Software
must set this bit for the required amount of time and then clear it to 0. If HOST is set
the controller appends a Low Speed End of Packet to the resume signaling when
RESUME is cleared.
Even/Odd Reset (ODD_RST): Setting this clears all BDT ODD ping/pong bits.
USB Enable (USBE): Setting this bit enables the controller and resets all ODD bits to
the BDT. If HOST is set, SOFs are generated by the controller.
Description
Reserved
Endpoint (ENDP): Encodes the endpoint address that received or transmitted the
previous token. This allows the CPU to determine which BDT entry was updated by the
last USB transaction.
Transmit (TX): When set, indicates the last BDT updated was for a transmit. When
cleared, the last transaction was a receive data transfer.
Odd (ODD): When set, last buffer descriptor update was in the odd bank of the BDT.
Reserved
As a host, the controller is executing a USB token and no more token
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