Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 134
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
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Manufacturer
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Price
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Z32AN Series Data Sheet
16.2.5.3
16.2.5.4
16.2.5.5
DS0200-003
This forms a 16-bit value that is compared to Tx.COUNT. When a match occurs, the PWM output changes
state. The PWM output value is set in TxCTL.TPOL.
15:00
31:16
15:00
31:01
31:09
05:03
Offset 008h: T16_x_PWM – Timer PWM
Offset 00Ch: T16_x_INT – Timer Interrupt
Offset 010h: T16_x_CTL – Timer Control
Bits
Bits
Bits
00
07
06
08
RW1C
Type
Type
Type
RW
RW
RW
RW
RW
RO
RO
RO
Reset
Reset
Reset
FFFFh
0000h
0h
0
0
0
0
0
0
Compare Value (VALUE): Stores the current 16-bit Compare value, which is used to
set the maximum count value which initiates a Timer Reload to 0001h.
Description
Reserved
PWM Value (VALUE): Stores the 16-bit value that is compared to the current 16-bit
timer count.
Description
Reserved
Clear Interrupt (CLR): When written to ‘1’, clears the interrupt.
Description
Reserved
Enable (EN): When set, the timer is enabled to count.
Input/Output Polarity (POL): This is a function of the current operating mode of the
timer. See section 16.2.2.
Pre-scale Value (PRES): The timer input clock is divided by 2
0000: Divide by 1
0001: Divide by 2
0010: Divide by 4
0011: Divide by 8
0100: Divide by 16
0101: Divide by 32
0110: Divide by 64
0111: Divide by 128
1000: Divide by 256
1001: Divide by 512
1010: Divide by 1024
1011: Divide by 2048
1100: Divide by 4096
1101 - 1111: undefined
PRES
, as shown below.
Page 121
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