Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 150

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.5
DS0200-003
31:08
07:06
05:04
Offset 008h: UARTx_FCR – UART FIFO Control Register
Bits
03
02
01
00
Type
WO
WO
WO
WO
WO
RO
RO
Reset
00
0
0
0
0
0
0
Description
Reserved
Trigger Level (TRIG): See below:
Valid only if FIFO is enabled.
Reserved
DMA Enable (DMA): When set, DMA is enabled.
Clear Transmit FIFO (CLRTXF): Writes of ‘1’ clear the transmit FIFO and resets the
transmit FIFO pointers. Valid only if the FIFOEN is set. Writes of ‘0’ have no effect.
Clear Receive FIFO (CLRRXF): Writes of ‘1’ clear the receive FIFO, clear the receive
error FIFO, and resets the receive FIFO pointers. Valid only if FIFOEN is set. Writes of
‘0’ have no effect.
FIFO Enable (FIFOEN): 0 = Transmit and receive FIFOs are disabled. Transmit and
receive buffers are only 1 byte deep. 1 = Transmit and receive FIFOs are enabled. The
receive FIFO will not be enabled during Multi-drop Mode (UARTx_MCR.MDM is set).
 00 = Receive data interrupt/DMA request is generated when there is 1 byte in the
 01 = Receive data interrupt/DMA request is generated when there are 4 bytes in
 10 = Receive data interrupt/DMA request is generated when there are 8 bytes in
 11 = Receive data interrupt/DMA request is generated when there are 14 bytes in
receive FIFO. Transmit DMA request is generated when there is 1 or fewer bytes
in the transmit FIFO. Valid only if FIFO is enabled.
the FIFO. Transmit DMA request is generated when there are 4 or fewer bytes in
the transmit FIFO. Valid only if FIFO is enabled.
the FIFO. Transmit DMA request is generated when there are 8 or fewer bytes in
the transmit FIFO. Valid only if FIFO is enabled.
the FIFO. Transmit DMA request is generated when there are 14 or fewer bytes in
the transmit FIFO.
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