Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 70

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
8.12.2.2
8.12.2.3
DS0200-003
30:00
31:07
Bits
DMA_STAn – DMA Channel “n” Status Register
DMA_SRCn – DMA Channel “n” Source Register
Bits
31
06
05
04
03
02
01
00
Type
RW1C
RW1C
RW1C
RW1C
Type
RW
RO
RO
RO
RO
RO
Reset
Reset
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Time-Out (TO): When set, a time-out has occurred for this channel.
Reserved
Bus Error (BUS_ERR):
disabled.
Reload Status (RLOAD): When set, indicates a reload has occurred on this channel.
Count-to-Zero Status (CTZ): When set, a Count-to-Zero condition has occurred.
Pending (PEND): When set, indicates that a DMA request is pending for this channel.
Enable Status (EN):
configuration, address, and count registers for the channel may be altered. This bit
follows DMA_CFGN.EN. This bit automatically clears under the following conditions:
When this bit transitions from 1 to 0, DMA_CFGN.EN also clears (if not cleared already).
Description
Reserved
Address (ADDR): For peripheral transfers, address bits are fixed (see Table 8-1). For
memory transfers, if DMA_CFGN.SRC_INC is ‘1’, the counter is incremented by 1, 2, or
4, depending on the width of each AHB cycle.
DMA_CRLDN.EN = ‘1’, this is reloaded with the contents of DMA_SRLDN.
 Bus error (cleared immediately)
 Count-to-zero with RLOAD EN=0 (cleared at the end of the AHB R/W burst).
 EN CTRL cleared by programmer (cleared at the end of the AHB R/W burst).
When set, the channel is enabled.
When set, an AHB abort was received and the channel
When a count-to-zero occurs and
When cleared, the
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