Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 59

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
7.4.1.7
DS0200-003
There are 10 memory controller chip select timing registers. The above table lists the offsets, and the table
below describes the bits in each register. All timing parameters are based on hclk when FLCLKBTEN = ‘0’,
and based on flclk when FLCLKBTEN = ‘1’.
31:30
29:27
26:24
23:20
19:16
14:11
10:08
07:04
MEMC_TIMn – Memory Controller nCS[“n”] Timing Registers
Bits
15
Type
RW
RW
RW
RW
RW
RW
RO
RO
Reset
111
111
111
Fh
Fh
Fh
0
0
Offset
03Ch
04Ch
040h
044h
048h
Description
Reserved
NRWI: Number of hclks of the minimum time after a read before a subsequent write
cycle, an access on a different chip select, or data bus clamping can occur.
NWH: Number of clocks of the write cycle hold time.
Write Access Time (NWA): Number of clocks:
NWS: Number of clocks for write cycle setup time (before nWE goes active).
Reserved
NRPA: Number of clocks for read access time of sequential access of a page burst
read.
NRW: Number of hclks of the read cycle hold time.
Read Access Number (NRA): Number of clocks for read access time.
 FLCLKBTEN = ’0’ → 000: 0 hclk cycles, 001: 1 hclk cycles, … 111: 7 hclk cycles
 FLCLKBTEN = ’1’ → 000: 1 flclk cycle, 001: 2 flclk cycles, … 111: 7flclk cycles
 FLCLKBTEN=0 & NWS[0] = 0 → 000: 0 hclks, 001: 1 hclk, … 111: 7 hclks
 FLCLKBTEN=0 & NWS[0] = 1 → 000:
 FLCLKBTEN=1 → 000: 1 flclk, 001: 2 flclks, …, 111: 8 flclks
 FLCLKBTEN = ’0’ → 0000: 1 hclk cycle, 0001: 2 hclk cycles, … 1111: 16 hclk
 FLCLKBTEN = ’1’ → 0000: 1 flclk cycle, 0001: 2 flclk cycles, … 1111: 16 flclk
 FLCLKBTEN=’0’ => 0h: 0 hclks, 1h:
 FLCLKBTEN=1 => 0000: 1 flclk cycle, 0001: 2 flclk cycles, …, 1111: 16 flclk
 0000: 1 cycle, 0001: 2 cycles, 0010: 3 cycles, … 1111: 16 cycles
 FLCLKBTEN=0 & Page=0 & NRS[0]=0 → 000: 0 hclks, 001: 1 hclk, …, 111: 7
 FLCLKBTEN=0 & Page=0 & NRS[0]=1 → 000:
 FLCLKBTEN=0 and Page=1 → 000: 0 hclk cycle, 001: 1 hclk cycles, …, 111: 7
 FLCLKBTEN=1 → 000: 0 flclk cycle, 001: 1 flclk cycles, …, 111: 7 flclk cycles
 FLCLKBTEN=0 → 0h: 1 hclk, 1h: 2 hclks, …, Fh: 16 hclks
 FLCLKBTEN=1 → 0h: 1 flclk, 1h: 2 flclks, …, Fh: 16 flclks
…, 111: 7
cycles
cycles
7
cycles
hclks
hclks, …, 111: 7
hclk cycles
1
/
2
hclk cycles
Chip Select
1
/
2
0
1
2
3
4
hclks
1
/
2
hclks
Offset
05Ch
050h
054h
058h
060h
Chip Select
1
/
1
2
/
2
hclks, 2h: 1 hclks, 3h: 1
hclks, 001: 1
5
6
7
8
9
1
/
2
hclk, 001: 1
1
/
2
hclks, 010: 2
1
/
2
hclks, 010: 2
1
/
2
hclks…, Fh:
1
/
Page 46
2
hclks,
1
/
2