Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 24

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
3.5
3.5.1
DS0200-003
PMU Registers: (Base → FFFFE000h)
The PMU registers are reset by a hard reset, unless otherwise noted in the register description. Most of the
system and registers are reset by a system reset, but the PMU and Watchdog Timer are exceptions.
Offset 000h: PMUPLL – PMU PLL Register
31:28
27:24
23:16
15:02
Bits
01
00
Type
RW
RW
RW
RW
RO
RO
Offset
000h
004h
008h
00Ch
014h
01Ch
Reset
13h
1h
0h
0
0
0
Description
PLL Output Divider "P" (OUTDIVP): Determines how much the pll_clk is divided
after frequency multiplication.
PLL Input Divider “N” (INDIVN): Determines how much the crystal_clk is divided
before frequency multiplication. This must result in a frequency above 12 MHz
PLL Multiplier “M” (MULTM): Determines how much the frequency is multiplied.
This must result in a frequency below 500 MHz and greater than 225 MHz
Reserved
PLL Lock (PLL_LOCK): When cleared, not locked. When set, locked.
PLL Power Enable (PLL_ENJ): When cleared, power down. When set, power up.
PMURESET
 0000: pll_clk is divided by 1
 0001: plll_clk is divided by 2
 ...
 1111: pll_clk is divided by 16
 0000: crystal_clk is divided by 1
 0001: crystal_clk is divided by 2
 ...
 1111: crystal_clk is divided by 16
 00h: ILLEGAL SETTING
 01h: frequency multiplier factor is 2
 02h: frequency multiplier factor is 3
 ...
 FFh: frequency multiplier factor is 256
PMUCKEN
Register
PMUCFG
PMUPLL
PMUCLK
PMUID
Description
PMU PLL Register
PMU Clock Control Register
PMU Clock Enable Register
PMU Reset Register
PMU ID Register
PMU Configuration Register
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