Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 66

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
8.9
8.10 Memory-to-Memory DMA
8.11 External DMA
DS0200-003
Register Accesses Restrictions
Any register can be written while a channel is disabled. When DMA_STAN.EN is set to ‘1’, the channel is
enabled. As an active channel can be in the middle of read/write burst, DMA_SRCN, DMA_DESTN, or
DMA_CNTN must not be written.
DMA_STAN.EN must be polled to verify that the channel is disabled. When clearing DMA_CFGN.EN,
perform a read-modify-write to ensure that other bits of DMA_CFGN are not modified.
automatically disabled if there is an AHB bus error, or a count-to-zero condition occurs with
DMA_CRLDN.EN cleared. If these occur, EN and EN of DMA_CFGN are cleared automatically.
Memory-to-memory transfers are performed as if the request is always active. Therefore, assign a lower
priority to channels executing memory-to-memory transfers to prevent starvation of other DMA channels.
An external DMA transfer is initiated by asserting nTxREQ. Figure 8-1 displays the nTxACK waveform to an
external device. nTxACK is asserted at least 1 hclk before nCS, and de-asserts at least 4 hclks after the de-
assertion of nCS. The polarity is selected in DMA_CTRL.
Note: The above figure assumes active low signals
Figure 8-1: Acknowledge Waveform
A DMA channel can be disabled by clearing DMA_CFGN.EN.
A channel is
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