Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 162

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
18.8 SPI Baud Rate Generator (BRG)
18.9 SPI Registers (Base: SPI0→FFFEE00h, SPI1→FFFEF000h)
18.9.1 Offset 00h: SPI_DAT – SPI Data Register
DS0200-003
In master mode, the BRG creates a lower frequency serial clock (SCK) for data transmission
synchronization between the Master and the external Slave. The input to the Baud Rate Generator is the
hclk. The SPI Baud Rate register is a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The
reload value must be greater than or equal to 0002H for SPI operation (maximum baud rate is hclk
frequency divided by 4). The SPI baud rate is calculated using the following equation (for the special case
BRG = 0x0000 substitute 2**16 for BRG in the equation):
When the SPI is disabled, the Baud Rate Generator can function as a CONTINUOUS mode 16-bit timer with
interrupt on time-out.
Follow the steps below to configure Baud Rate Generator as a timer with interrupt on time-out:
31:16
15:00
Bits
1.
2.
3.
Clear SPI_CTL.SPIEN to ‘0’
Load the appropriate 16-bit count value into the SPI Baud Rate register, BRG[15:0]
Set SPI_CTL.BIRQ to ‘1’
Type
RW
Offset
RO
000h
004h
008h
00Ch
010h
014h
018h
Reset
Undef
0
SPI_DIAG
Register
SPI_MOD
SPI_DMA
SPI_DAT
SPI_BRG
SPI_CTL
SPI_STA
Description
Reserved
Data (DATA): Stores outgoing (transmit) data and incoming (received) data. With SPI
configured as a master, writing data to this register initiates transmission. With SPI
configured as a slave, writing data to this register loads the shift register in preparation
for the next data transfer with the external master.
Data is shifted out starting with bit 15. The last bit received will reside in bit position 0.
When the character length is less than 16 bits (as set by SPI_MOD.NUMBITS), the
transmit character must be left justified. A received character of less than 16 bits is
right justified (last bit received will be in bit position 0).
Description
SPI Data Register
SPI Control Register
SPI Status Register
SPI Mode Register
SPI Diagnostic State Register
SPI Baud Rate Register
SPI DMA Register
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