Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 175

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
19.8 Registers (Base → FFFBD000h)
19.8.1 Offset 000h: USB_PER_ID – Peripheral ID Register
DS0200-003
31:08
07:00
Bits
Type
0C0h – 0FCh
RO
RO
Offset
00Ch
01Ch
08Ch
09Ch
0A0h
0A4h
0A8h
0ACh
0B0h
0B4h
000h
004h
008h
010h
014h
018h
080h
084h
088h
090h
094h
098h
Reset
04h
0
Description
Reserved
Configuration number (ID): Peripheral is the USB block FS/LS USB Core.
USB_ENDPT_CTRL
USB_BDT_PAGE1
USB_BDT_PAGE2
USB_BDT_PAGE3
USB_OTG_ISTAT
USB_OTG_STAT
USB_OTG_CTRL
USB_ADD_INFO
USB_ID_COMP
USB_OTG_IEN
USB_FRAMEH
USB_FRAMEL
USB_PER_ID
USB_TOKEN
USB_ESTAT
USB_ISTAT
USB_ADDR
USB_STAT
USB_CTRL
USB_SOFT
USB_REV
USB_EEN
Address
USB_IEN
Description
Peripheral ID Register
Peripheral ID complement Register
Peripheral revision register
Peripheral additional info register
OTG Interrupt Status Register
OTG Interrupt Control Register
OTG Status Register
OTG Control register
Interrupt status register
Interrupt enable register
Error interrupt status register
Error interrupt enable register
Status register
Control register
Address register
Buffer Descriptor Table Page Register 1
Frame number low register
Frame number high register
Token register
SOF threshold register
Buffer Descriptor Table Page Register 2
Buffer Descriptor Table Page Register 3
Endpoint control register
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