Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 6

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
DS0200-003
Chapter 6: Interrupt Controller (INTC)......................................................................... 21
Chapter 7: External Bus Interface (EBI) ....................................................................... 29
5.2 Accesses............................................................................................................................................... 18
5.3 Restricted / Reserved Addresses...................................................................................................... 18
5.4 ROM/SRAM Remapping .................................................................................................................... 18
5.5 Internal SRAM....................................................................................................................................... 18
5.6 Internal ROM and Boot Program...................................................................................................... 19
6.1 Interrupt Channels and Sources....................................................................................................... 21
6.2 Interrupt Priority.................................................................................................................................... 21
6.3 Configuring the Interrupt Controller ................................................................................................ 22
6.4 ISR Invocation ...................................................................................................................................... 22
6.5 ISR Return from Interrupt .................................................................................................................... 22
6.6 Interrupt Nesting.................................................................................................................................. 22
6.7 Interrupt Latching ............................................................................................................................... 23
6.8 Registers: Base → FFFFF000h.............................................................................................................. 23
7.1 Asynchronous Memory Controller ................................................................................................... 29
7.2 SDRAM Controller................................................................................................................................ 34
7.3 Example Configurations .................................................................................................................... 37
7.4 Registers (Base → FFFF8000h)............................................................................................................ 41
5.5.1
5.5.2
5.5.3
5.6.1
5.6.2
5.6.3
5.6.4
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10 Offset 024h: INTC_SWINT_SET – Software Interrupt Set Register ...................................25
6.8.11 Offset 028h: INTC_SWINT_CLR – Software Interrupt Clear Register .............................26
6.8.12 INTC_VECN – Channel N Vector Register ......................................................................26
6.8.13 INTC_CFGN – Channel N Configuration Register..........................................................27
6.8.14 Offset F00h: INTC_IVEC – IRQ Vector Register ...............................................................27
6.8.15 Offset F04h: INTC_FVEC – FIQ Vector Register ...............................................................27
6.8.16 Offset F08h: INTC_IEND – IRQ End-of-Interrupt Register ................................................28
6.8.17 Offset F0Ch: INTC_FEND – FIQ End-of-Interrupt Register ...............................................28
7.1.1
7.1.2
7.1.3
7.1.4
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Clock Disable....................................................................................................................18
Zeroization .........................................................................................................................18
Address FFFF8068h: INT_SRAM_CLR – Internal SRAM Clear Register ............................18
Boot locations ...................................................................................................................19
External Memory Image Format .....................................................................................19
Boot Sequence.................................................................................................................20
Boot ROM MMU Table......................................................................................................20
Offset 000h: INTC_EN – Interrupt Controller Enable Register ........................................23
Offset 004h: INTC_ESET – Interrupt Controller Enable Set Register ...............................24
Offset 008h: INTC_ECLR – Interrupt Controller Enable Clear Register..........................24
Offset 00Ch: INTC_DFLT – Default Vector Register ........................................................24
Offset 010h: INTC_ISTA – Interrupt Status Register..........................................................24
Offset 014h: INTC_RSTA – Raw Interrupt Status Register................................................24
Offset 018h: INTC_IDBG – IRQ Processor Debug Register .............................................25
Offset 01Ch: INTC_FDBG – FIQ Processor Debug Register............................................25
Offset 020h: INTC_SWINT – Software Interrupt Register.................................................25
Programmable Features..................................................................................................29
Asynchronous Single Read and Write Transactions ......................................................31
Asynchronous Page Read Transactions.........................................................................32
Clock Divided Transactions .............................................................................................33
Operation..........................................................................................................................34
Address Mapping .............................................................................................................34
Supported Configurations ...............................................................................................35
SDRAM Performance .......................................................................................................35
Open Bank Policy .............................................................................................................35
Power Saving Modes .......................................................................................................36
Pin Multiplexing .................................................................................................................36
Programmer’s Guide........................................................................................................36
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