Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 42

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 7: External Bus Interface (EBI)
7.1
7.1.1
7.1.1.1
7.1.1.2
7.1.1.3
DS0200-003
The EBI consists of the following blocks:
MA[23:0], MD[15:0], SA[22:0], and SD[15:0] are all actively driven low whenever idle.
Asynchronous Memory Controller
This controller interfaces to up to 10 external memory or I/O devices. Features:
Each chip select has a number of programmable features which can be configured via MEMC_CFGN. Some
are listed below.
The READY pin can be used to extend the read and write access times until signaled by an external slave
device. Two configuration bits are provided for each chip select: one enables or ignores the READY pin; the
other sets the polarity as READY or nREADY. READY can only be used for the primary and not the
secondary or the secondary and not the primary. This is because each bus has its own controller and can
act independently of the other (Primary and Secondary accesses can occur at the same time). If HREADY is
enabled for Chip Selects on both buses, conflicts can occur since accesses to peripherals which use the
HREADY line could occur at the same time. There is no internal arbitration for the HREADY pin. Each Chip
Select will respond to the HREADY if programmed to do so.
8-bit and 16-bit devices are supported. Both can be accessed transparently over AHB with byte, half-word,
word and burst accesses.
16-bit devices can be accessed with two write enables and no byte enable, or with a single write enable and
two byte enables. The table below shows the muxing which can be done to support these cases.
Programmable Features
Ready/Wait
Device Data Width
Byte Control Style







External Memory Controller (MEMC): The primary bus supports standard asynchronous
memories (such as SRAM, ROM, Flash, etc.), I/O devices, and asynchronous PSRAM.
SDRAM Controller: This provides direct interfacing to standard SDRAM.
Asynchronous memory support (SRAM, ROM, Flash, PSRAM, Flash etc.)
Support for I/O devices which utilize an asynchronous SRAM-like interface
Programmable setup, hold, access and burst timings for each chip select
Optional ready/wait line for each chip select
Support for single asynchronous reads and writes, and asynchronous page reads.
Byte Control Style Settings
1 (16-bit)
0 (8-bit)
Width
Table 7-1: Pin Functions vs. Control Style
0 (no BE)
0 (no BE)
1 (BE)
1 (BE)
Style
nWEU
nWEU
nBEU
nBE
1
Z32AN Series Pin Function
nWEL
nWEL
nWE
nWE
nWE
A[0]
nBEL
A[0]
A[0]
0
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