Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 184

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
19.8.23 USB_ENDPTn_CTRL – Endpoint “N” Control Registers
DS0200-003
These registers contain endpoint control bits for each of the 16 endpoints available. Offsets for each
endpoint are above, and a description of the register is shown below.
31:08
Bits
03
02
07
06
05
04
01
00
Offset
RW
RW
Type
C0h
C4h
C8h
CCh
RW
RW
RW
RW
RW
RO
RO
CTL_DIS
X
X
X
1
Reset
Endpoint
0
0
0
0
0
0
0
0
0
0
1
2
3
RXE
Receive Enable (RXE): See Table 19-3.
Transmit Enable (RXE): See Table 19-3.
Table 19-3: Endpoint Enable / Direction Control
0
0
1
1
Description
Reserved
Host Without Hub (NOHUB): Host mode only. Only present in the control register
for endpoint 0. When set, allows the host to communicate to a directly connected low
speed device. When cleared host produces the PRE_PID then switches to low speed
signaling when sending a token to a low speed device.
Retry Disable (RETRY_DIS): Host mode only. Only present in the control register
for endpoint 0. When set, host does not retry NAKed transactions. The BDT PID field
will be updated with the NAK PID, and the token done interrupt is set. When cleared,
NAKed transactions are retried by hardware. This bit must be set when the host is
attempting to poll an interrupt endpoint.
Reserved
Control Disable (CTL_DIS): See Table 19-3.
Stall (STALL): When set, an endpoint is stalled. This bit has priority over all other bits
in this register, but is only valid if TXE=1 or RXE=1. Any access to this endpoint will
cause the controller to return a STALL handshake.
Handshake (HSHK):
transaction to this endpoint. Not set for an isoch endpoint.
Offset
DCh
D0h
D4h
D8h
TXE
0
1
0
1
Endpoint Enable/Direction Control
Disable Endpoint
Enable Endpoint for TX transfers only
Enable Endpoint for RX transfers only
Enable Endpoint for both RX and TX transfers
Endpoint
4
5
6
7
When set, the endpoint performs handshaking during a
Offset
ECh
E0h
E4h
E8h
Endpoint
10
11
8
9
Offset
FCh
F0h
F4h
F8h
Endpoint
12
13
14
15
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