Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 68

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
8.12.2 Per-Channel Registers
8.12.2.1
DS0200-003
28:24
21:20
DMA_CFGn – DMA Channel “n” Config Register
Bits
31
30
29
23
22
19
18
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
10Ch
11Ch
100h
104h
108h
110h
114h
118h
Ch0
Reset
00000
00
0
0
0
0
0
0
0
12Ch
13Ch
120h
124h
128h
130h
134h
138h
Ch1
Description
Count-to-Zero Interrupt Enable (CTZ_IEN): When set, the IPEND goes active
whenever a Count-to-Zero event occurs.
Status Interrupt Enable (STA_IEN):
DMA_STAN.EN transitions from 1 to 0.
Reserved
Burst Size (BURST): The number of bytes to be transferred into and out of the DMA
FIFO in handling a single burst.
Reserved
Destination Increment Enable (DINCR):
DMA_DESTN on every AHB transaction. Forced to 0 for DMA transmit to peripherals.
Destination Width (DWIDTH): Indicates the width of the each AHB transaction to
the destination peripheral or memory.
Reserved
Source Increment Enable (SINCR): When set, enables incrementing of DMA_SRCN
upon every AHB transaction. Forced to 0 for DMA receive from peripherals.
14Ch
15Ch
140h
144h
148h
150h
154h
158h
Ch2
 00000: 1 byte
 00001: 2 bytes
 ...
 11111: 32 bytes
 00: byte
 01: half-word
 10: word
 11: reserved
16Ch
17Ch
160h
164h
168h
170h
174h
178h
Ch3
Offsets
18Ch
19Ch
180h
184h
188h
190h
194h
198h
Ch4
1A0h
1A4h
1A8h
1ACh
1BCh
1B0h
1B4h
1B8h
Ch4
1DCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
Ch6
1ECh
1FCh
1E0h
1E4h
1E8h
1F0h
1F4h
1F8h
Ch7
When set, IPEND will go active whenever
When set, enables incrementing of
DMA_DRLDN
DMA_DESTN
DMA_SRLDN
DMA_CRLDN
DMA_CFGN
DMA_STAN
DMA_SRCN
DMA_CNTN
Register
Page 55