XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 120

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Each of these functional blocks is briefly discussed below. These functional blocks will be discussed in
considerable detail throughout this data sheet.
1.2.1
The purpose of the Clock Synthesizer block is to synthesize a 19.44MHz and a 155.52MHz clock signal from
an externally supplied 19.44MHz reference clock signal.
The Transmit STS-3 TOH and the Transmit STS-3c POH Processor blocks will use these clock signals as its
timing source, for transmitting the outbound STS-3 data either via the PECL interface (e.g., to the optical
transceiver) or via the Telecom Bus Interface, to the remote terminal.
1.2.2
The purpose of the Receive STS-3 PECL Interface and CDR Block is to perform the following functions.
• To receive an STS-3 electrical signal (which is of the PECL format) from either a system back-plane or from
an optical transceiver.
• As the Receive STS-3 PECL Interface block receives this electrical (data) signal, it will route this data-
stream to the “STS-3 Clock and Data Recovery (CDR) Block. This STS-3 CDR block will then generate a
155.52MHz clock and corresponding data signal, which will be routed to the Receive STS-3 TOH Processor
block for further processing.
1.2.3
The purpose of the “Receive STS-3 TOH Processor” block is to perform the following functions.
• To receive an STS-3 signal from the remote terminal via optical fiber and a PECL interface, or via the
“Receive STS-3 Telecom Bus Interface.
• To declare and clear the LOS, SEF, LOF and AIS-L defect conditions.
• To declare and clear the RDI-L, SD and SF defect conditions.
• To optionally transmit the AIS-P indicator (downstream, towards the Receive STS-3c POH Processor block)
upon declaration of the AIS-L, LOS, LOF, SD or SF defect conditions.
• To compute and verify the B1 and B2 bytes of the incoming STS-3 signal.
• To detect and increment performance monitor registers anytime it detects any B1 and B2 byte errors.
• To receive and process Section Trace messages via the J0 byte.
• To terminate the Transport Overhead (TOH) within the incoming STS-3 signal.
• To detect and increment performance monitor registers anytime it detects any REI-L events.
• To receive and process messages via the J0 byte.
• To terminate the Transport Overhead (TOH) within the incoming STS-3 signal.
• To byte de-interleave the STS-3 signal into 3 STS-1 SPE data-streams, and to route the resulting STS-1
SPE data-stream to each of the three (3) Receive SONET POH Processor block.
1.2.4
The purpose of the “Receive SONET POH Processor” block is to perform the following functions.
• To receive one of the three STS-1 signal (originally extracted from the incoming STS-3 signal) to terminate
the Path Overhead (POH).
• To declare and clear LOP-P, AIS-P, UNEQ-P, PLM-P, TIM-P, and the RDI-P defect conditions.
T
T
T
T
HE
HE
HE
HE
C
R
R
R
LOCK
ECEIVE
ECEIVE
ECEIVE
S
YNTHESIZER
STS-3 PECL I
STS-3 TOH P
SONET POH P
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
B
LOCK
ROCESSOR
NTERFACE AND
ROCESSOR
B
B
LOCK
LOCK
CDR B
120
LOCK
xr