XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 343

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
If the Receive STS-3 TOH Processor block receives two consecutive SONET frames that do have contain
any Framing Alignment byte errors, then it will clear the SEF Defect and will transition back into the “In-
Frame” state.
On the other hand, if the Receive STS-3 TOH Processor continues to detect incoming SONET frames (with
Framing Alignment errors) then it will continue to declare the “SEF” defect. If the Receive STS-3 TOH
Processor block continues to declare the “SEF Defect” for at least 3ms, then it will declare the “LOF Defect”.
At this time, the Receive STS-3 TOH Processor block will transition back into the “SEF = 1, LOF = 1” state.
The “SEF” and “LOF” declaration and clearance criteria are summarized, in some detail below.
2.3.1.3.5
The Receive STS-3 TOH Processor block is capable of declaring and clearing the SEF (Severely Erred
Frame) defect condition; as described below.
2.3.1.3.5.1
The Receive STS-3 TOH Processor block will declare the SEF defect condition anytime it detects Framing
Byte (A1 and A2) errors in four consecutive frames.
Whenever the Receive STS-3 TOH Processor block declares the SEF defect condition, then it will do the
following.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.3.5.2
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
RDI-L
B
B
RUR
1. It will indicate that it is declaring the SEF defect condition by setting Bit 1 (SEF Defect Declared),
R/O
2. It will generate the “Change of SEF Defect Condition Interrupt”. The Receive STS-3 TOH Processor
IT
IT
0
0
7
7
within the Receive STS-3 Transport Status Register – Byte 0” to “1”, as depicted below.
block will indicate that it is declaring the “Change of SEF Defect Condition” Interrupt by doing the
following.
a. Toggling the “INT*” output pin “LOW”.
b. b. Setting Bit 1 (Change of SEF Defect Condition Interrupt Status), within the Receive STS-3
THE SEF (SEVERELY ERRED FRAME) DEFECT DECLARATION AND CLEARANCE
CRITERIA
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
How the Receive STS-3 TOH Processor Block Declares the SEF Defect
S1 Byte
Transport Interrupt Status Register – Byte 0” to “1”, as illustrated below.
How the Receive STS-3 TOH Processor Block clears the SEF Defect Condition
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
6
6
Detection of
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Status
B
B
Error
RUR
R/O
IT
IT
0
0
4
4
343
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Status
Error
B
B
RUR
R/O
IT
IT
0
0
3
3
LOF Defect
LOF Defect
Change of
Condition
Declared
Interrupt
Status
B
B
RUR
R/O
IT
IT
0
0
2
2
SEF Defect
SEF Defect
Change of
Condition
Declared
Interrupt
Status
B
B
RUR
R/O
IT
IT
1
1
1
1
XRT94L33
LOS Defect
LOS Defect
Change of
Condition
Declared
Interrupt
Status
Rev.1.2.0.
B
B
RUR
R/O
IT
IT
0
0
0
0