XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 327
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 74 A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
The “TxPOHIns_n” line (in
Note:
•
“TxPOHEnable_n” pin “low”, then it should enter a “WAIT STATE” (e.g., where it waits for __ periods of
“TxPOHClk_n” to elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the
very first bit (e.g., the most significant bit) of the “outbound” S1 byte onto the “TxPOH_n” input pin, upon the
very next falling edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c
POH Processor” block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the S1 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 75 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the S1 byte into the “TxPOH Input Port”.
Figure 75 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “S1 byte” into the “TxPOH Input Port”
Whenever the “external circuit” samples the “TxPOHFrame_n” output pin “high” and also the
) is “dashed” because this controlling this signal is not necessary if the user has executed “STEP 2” above.
This “WAIT STATE” period is necessary because the S1 byte is the _ byte within the TOH.
XRT94L43 Device
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
327
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
XRT94L33
Rev.1.2.0.
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