XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 447

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
SELECTING THE CELL SIZE (NUMBER OF OCTETS PER CELL)
The XRT94L34 device permits the user to select the number of octets per cell that the Receive UTOPIA
Interface block will output, following each assertion of the RxUSoC output pin. Specifically, the user has the
following cell size options.
• If the UTOPIA Data Bus width is set to 8 bits then the user can choose:
• If the UTOPIA Data Bus width is set to 16 bits then the user can choose:
The user makes their selection by writing the appropriate data into bits 1 and 0 (Cell_Size_Sel[1:0]) within the
Receive UTOPIA Control Register, as depicted below.
Receive UTOPIA/POS-PHY Control Register – Byte 0 (Address = 0x0503)
The following table presents the relationship between the value of these bits and the number of octets/cell
that the Receive UTOPIA Interface block will process.
Table 23 The Relationship between the contents of Bits 1 and 0 (Cell_Size_Sel[1:0]) within the Receive
UTOPIA Control Register, and the number of octets per cell that will be processed by the Receive
UTOPIA Interface blocks following each assertion of the RxUSOC output pin
Once the user has implemented his/her selection for the cell size, then the Receive UTOPIA Interface block
will be configured to output “Cell Size” number of octets, per each assertion of “RxUSoC”.
2.3.5.1.2.2
ATM Forum documentation refers to both “Cell Level” and “Octet-Level” handshaking.
XRT94L33 only supports the “Cell-Level” Handshaking mode. Octet-level handshaking is NOT supported. In
the “Cell Level Handshaking mode, when the XRT94L33 sets the RxUClav output pin to a logic “1”, it means
that the RxFIFO contains at least one ATM cell’s worth of data that needs to be read out by the ATM Layer
Processor. However, when RxUClav toggles from “high” to “low” it indicates that the RxFIFO does not
contain any cells (following the one that is currently being read out of the Receive UTOPIA Interface block).
The ATM Layer processor is expected to poll the state of the RxUClav output pin towards the end of the
UTOPIA
Disable
Level 3
C
B
R/W
ELL
IT
1
7
_S
52 bytes (with no HEC byte in the cell), or
53 bytes (with either a dummy or actual HEC byte in the cell)
52 bytes (with no HEC byte in the cell), or
54 bytes (with either a dummy or actual HEC byte, and a stuff byte in the cell)
IZE
00
01
10
11
_S
EL
Multi-PHY
[1:0]
Cell Level Handshaking
Enable
Polling
B
R/W
IT
0
6
Back Polling
53 bytes/cell (only valid if the Receive UTOPIA Data Bus Width = 8 bits)
Back to
Enable
B
R/W
IT
0
5
Indication
Enable
Status
Direct
B
R/W
IT
0
4
N
UMBER OF
447
52 bytes/cell
54 bytes/cell
Receive UTOPIA/POS-PHY
Unused
B
R/W
B
IT
1
Data Bus Width
YTES
3
/C
ELLS
B
R/W
IT
1
2
B
R/W
IT
X
1
Cell Size[1:0]
However, the
XRT94L33
Rev.1.2.0.
B
R/W
IT
X
0